In a semiconductor storage device including a phase-change memory, a storage element is formed by using a Ge—Sb—Te based chalcogenide material (or phase-change material) containing at least antimony (Sb) and tellurium (Te) as a material of a recording layer. An element for selecting a memory cell is configured by using a vertical MOS transistor.
Japanese Unexamined Patent Application Publication No. 2008-160004 cited below discloses an array configuration in which phase-change memory cells using a chalcogenide material and a vertical MOS transistor are stacked. According to FIG. 3 in the patent document, four memory cells and a vertical transistor TR5 are disposed at points where a word line WL, a bit line BL and a source line SL intersect with each other. Each of the four memory cells has a configuration in which a phase-change element and a vertical transistor are connected in parallel with each other, and are formed on a side wall of a hole (hereinafter, referred to as “interconnect hole”) disposed in a stacked layer. These four memory cells are connected in series with the vertical transistor TR5. The word line WL is connected to a gate electrode of the vertical transistor TR5.